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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-09 20:48:37 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 15:44:19 +0000 |
| commit | 349e08535a7666cabe52ebc331e3bce5468b786b (patch) | |
| tree | 6e337227e7450ac1d931ac61eaf939ae936ad50c /src/southbridge/intel/i82801jx/bootblock.c | |
| parent | 7b9c139ac26eded525980e896b354c99c08cdca7 (diff) | |
| download | coreboot-349e08535a7666cabe52ebc331e3bce5468b786b.tar.xz | |
sb/intel/i82801jx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/bootblock.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 6252712eba..cc685c4544 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include "i82801jx.h" static void enable_spi_prefetch(void) { @@ -31,4 +32,8 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { enable_spi_prefetch(); + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA, + (uintptr_t)DEFAULT_RCBA | 1); } |