diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-07-21 10:08:25 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-21 14:46:13 +0000 |
| commit | c3198543b690fbdeda0f1e1ffaf78048fe765ec0 (patch) | |
| tree | e290487cbf5c37ec549d4baf5dc33a1141a48415 /src/southbridge/intel/i82801jx/chip.h | |
| parent | 8e39009c57dc92e6970a812ec82a2cee4cb6ced5 (diff) | |
| download | coreboot-c3198543b690fbdeda0f1e1ffaf78048fe765ec0.tar.xz | |
soc/intel/skylake: Perform LPC offset read after lockdown operation
This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/chip.h')
0 files changed, 0 insertions, 0 deletions