diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 02:09:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 00:12:17 +0000 |
| commit | 2048cb43863f014fedc4ff44233d49410f0cee5e (patch) | |
| tree | 1be140c2bf5bd48f278039d1c32d5fa382379a86 /src/southbridge/intel/i82801jx/i82801jx.c | |
| parent | efd23d92efb982f74b8473201bc93b1c0ad64bc8 (diff) | |
| download | coreboot-2048cb43863f014fedc4ff44233d49410f0cee5e.tar.xz | |
sb/intel/i82801jx: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/i82801jx.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.c | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index b4ffcfaba9..a332ec079b 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -34,7 +34,6 @@ static void i82801jx_pcie_init(const config_t *const info) { struct device *pciePort[6]; int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ - u32 reg32; /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { @@ -43,26 +42,21 @@ static void i82801jx_pcie_init(const config_t *const info) printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } - reg32 = pci_read_config32(pciePort[i], 0x300); - pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_or_config32(pciePort[i], 0x300, 1 << 21); pci_write_config8(pciePort[i], 0x324, 0x40); } if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { for (i = 0; i < 6; ++i) { if (pciePort[i]->enabled) { - reg32 = pci_read_config32(pciePort[i], 0xe8); - reg32 |= 1; - pci_write_config32(pciePort[i], 0xe8, reg32); + pci_or_config32(pciePort[i], 0xe8, 1); } } } for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ - reg32 = pci_read_config32(pciePort[i], 0x300); - reg32 |= 0x3 << 16; - pci_write_config32(pciePort[i], 0x300, reg32); + pci_or_config32(pciePort[i], 0x300, 0x3 << 16); } /* Set slot implemented, slot number and slot power limits. */ @@ -88,10 +82,8 @@ static void i82801jx_pcie_init(const config_t *const info) } /* Lock R/WO ASPM support bits. */ - for (i = 0; i < 6; ++i) { - reg32 = pci_read_config32(pciePort[i], 0x4c); - pci_write_config32(pciePort[i], 0x4c, reg32); - } + for (i = 0; i < 6; ++i) + pci_update_config32(pciePort[i], 0x4c, ~0, 0); } static void i82801jx_ehci_init(void) |