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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 02:46:39 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:17:50 +0000 |
| commit | 89739baf531e26dc81420df4f943bf8c163a0c0d (patch) | |
| tree | 61b363d8d6681e93af4d65bf7f0fd0276fa4bc8c /src/southbridge/intel/i82801jx/lpc.c | |
| parent | 4d2db06ab5f52bd283673c08b40b3b87600d0674 (diff) | |
| download | coreboot-89739baf531e26dc81420df4f943bf8c163a0c0d.tar.xz | |
{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits
We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index fceeb3f80e..a8b53706c1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -361,7 +361,9 @@ static void lpc_init(struct device *dev) printk(BIOS_DEBUG, "i82801jx: %s\n", __func__); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ i82801jx_enable_apic(dev); |