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authorPatrick Rudolph <siro@das-labor.org>2018-10-01 19:17:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:35:25 +0000
commit45022ae056cdbf58429b77daf2da176306312801 (patch)
tree4218666e3c14e41232778c4ceff301292b3c61d9 /src/southbridge/intel/i82801jx
parent33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff)
downloadcoreboot-45022ae056cdbf58429b77daf2da176306312801.tar.xz
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801jx/Makefile.inc1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index cb5b12fcd0..e56d692fb3 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -22,7 +22,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select IOAPIC
select HAVE_USBDEBUG
- select HAVE_HARD_RESET
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc
index d6a3a7ddf5..1053659d68 100644
--- a/src/southbridge/intel/i82801jx/Makefile.inc
+++ b/src/southbridge/intel/i82801jx/Makefile.inc
@@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
-ramstage-y += ../i82801gx/reset.c
ramstage-y += ../i82801gx/watchdog.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c