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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-03 07:30:26 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-14 14:08:57 +0000 |
| commit | de640781020b10e72dd6a5cda26cab10932e94fe (patch) | |
| tree | f3e43318b33a10918c906458e6b03b2a2194d7ee /src/southbridge/intel/i82801jx | |
| parent | 91c47c0deac054d5b949d1bf1be7c0e7cbf7d545 (diff) | |
| download | coreboot-de640781020b10e72dd6a5cda26cab10932e94fe.tar.xz | |
bootblock: Provide some common prototypes
The split of bootblock initialisation to cpu, northbridge and
southbridge is not specific to intel at all, create new header
<arch/bootblock.h> as AMD will want some of these too.
Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index b6016793c2..567679ebcc 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ +#include <arch/bootblock.h> #include <device/pci_ops.h> -#include <cpu/intel/car/bootblock.h> #include "i82801jx.h" static void enable_spi_prefetch(void) |