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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-28 10:29:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:23:29 +0000
commitca4ff25290c099152ee9b2b53df6eb0d71ef0823 (patch)
tree2db94efb2d732c4f3c834eae81825c55e1d63d81 /src/southbridge/intel/i82801jx
parentb9d2e228b63c898383f1f6e6bd5e02b018ff31af (diff)
downloadcoreboot-ca4ff25290c099152ee9b2b53df6eb0d71ef0823.tar.xz
sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register
Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
-rw-r--r--src/southbridge/intel/i82801jx/hdaudio.c3
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.c6
-rw-r--r--src/southbridge/intel/i82801jx/pcie.c4
-rw-r--r--src/southbridge/intel/i82801jx/usb_ehci.c6
4 files changed, 4 insertions, 15 deletions
diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c
index 1711de9ae3..5da7ce547f 100644
--- a/src/southbridge/intel/i82801jx/hdaudio.c
+++ b/src/southbridge/intel/i82801jx/hdaudio.c
@@ -247,8 +247,7 @@ static void azalia_init(struct device *dev)
pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c
index e55735b4a1..f3c899cad5 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -13,12 +13,8 @@ typedef struct southbridge_intel_i82801jx_config config_t;
static void i82801jx_enable_device(struct device *dev)
{
- u32 reg32;
-
/* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
}
static void i82801jx_early_settings(const config_t *const info)
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index dba1a6519e..df3140a543 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -20,9 +20,7 @@ static void pci_init(struct device *dev)
printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
/* Enable Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index 03b314a10d..45737a535e 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -11,12 +11,8 @@
static void usb_ehci_init(struct device *dev)
{
- u32 reg32;
-
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
printk(BIOS_DEBUG, "done.\n");
}