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authorAngel Pons <th3fanbus@gmail.com>2020-12-05 20:43:00 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-12-11 15:12:47 +0000
commit79b2a150c7a18a61604b0d81f52a7c6ad8522b60 (patch)
tree35fdf0dcfa4e0eaf2605c4f0c62cf2690ebcd409 /src/southbridge/intel/i82801jx
parent30ff00650a7129475bf01ce9d258ac27b59c786b (diff)
downloadcoreboot-79b2a150c7a18a61604b0d81f52a7c6ad8522b60.tar.xz
sb/intel/x/smbus.c: Factor out common code
Since common smbus.c gets built for romstage as well, create a new file to hold this common code. Account for ICH7 not having a memory BAR, too. Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
-rw-r--r--src/southbridge/intel/i82801jx/smbus.c70
1 files changed, 1 insertions, 69 deletions
diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c
index 2e2491aad5..11a3daa799 100644
--- a/src/southbridge/intel/i82801jx/smbus.c
+++ b/src/southbridge/intel/i82801jx/smbus.c
@@ -8,6 +8,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
+#include <southbridge/intel/common/smbus_ops.h>
#include "i82801jx.h"
static void pch_smbus_init(struct device *dev)
@@ -16,75 +17,6 @@ static void pch_smbus_init(struct device *dev)
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
}
-static int lsmbus_read_byte(struct device *dev, u8 address)
-{
- u16 device;
- struct resource *res;
- struct bus *pbus;
-
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
-
- return do_smbus_read_byte(res->base, device, address);
-}
-
-static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
-{
- u16 device;
- struct resource *res;
- struct bus *pbus;
-
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
- return do_smbus_write_byte(res->base, device, address, data);
-}
-
-static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf)
-{
- u16 device;
- struct resource *res;
- struct bus *pbus;
-
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
- return do_smbus_block_write(res->base, device, cmd, bytes, buf);
-}
-
-static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
-{
- u16 device;
- struct resource *res;
- struct bus *pbus;
-
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
- return do_smbus_block_read(res->base, device, cmd, bytes, buf);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
- .block_read = lsmbus_block_read,
- .block_write = lsmbus_block_write,
-};
-
-static void smbus_read_resources(struct device *dev)
-{
- struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = CONFIG_FIXED_SMBUS_IO_BASE;
- res->size = 32;
- res->limit = res->base + res->size - 1;
- res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
- IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- /* Also add MMIO resource */
- res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
-}
-
static struct device_operations smbus_ops = {
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,