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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-17 23:37:49 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 09:19:10 +0000 |
| commit | 0c1dd9c84188cc150a05302cc9b4af476a761d2b (patch) | |
| tree | cf8249cc3ba689e903c64d926c162c1e1f742d78 /src/southbridge/intel/i82801jx | |
| parent | bc1cb38ce15e059988263b04c0ea751ddf4b052d (diff) | |
| download | coreboot-0c1dd9c84188cc150a05302cc9b4af476a761d2b.tar.xz | |
ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/nvs.h | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/smihandler.c | 4 |
3 files changed, 7 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index c36009ed0a..2533d8cc72 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -497,9 +498,9 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -static void southbridge_inject_dsdt(const struct device *dev) +void southbridge_inject_dsdt(const struct device *dev) { - global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index c4879189ee..48a7d87fe1 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -4,7 +4,7 @@ #define SOUTHBRIDGE_INTEL_I82801JX_NVS_H #include <stdint.h> -typedef struct { +struct __packed global_nvs { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ u8 smif; /* 0x02 - SMI function call ("TRAP") */ @@ -96,8 +96,6 @@ typedef struct { u8 dock; /* 0xf0 - Docking Status */ u8 bten; u8 rsvd13[14]; -} __packed global_nvs_t; - -void acpi_create_gnvs(global_nvs_t *gnvs); +}; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 00b3ffaf72..af242aaf19 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -18,7 +18,7 @@ u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +struct global_nvs *gnvs = (struct global_nvs *)0x0; void *tcg = (void *)0x0; void *smi1 = (void *)0x0; @@ -41,7 +41,7 @@ int southbridge_io_trap_handler(int smif) void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { - gnvs = *(global_nvs_t **)0x500; + gnvs = *(struct global_nvs **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; *smm_done = 1; |