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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-01 11:29:50 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-01 11:25:07 +0000 |
| commit | c4e41937150beab78ba5d492b7b22799d20a0ee4 (patch) | |
| tree | f8248eb3b2988bc5d3384b96f87bb848f6876134 /src/southbridge/intel/i82801jx | |
| parent | 1956a00953d8eac277b0eb508fcfe60c8f4e1141 (diff) | |
| download | coreboot-c4e41937150beab78ba5d492b7b22799d20a0ee4.tar.xz | |
src: Add missing include <stdint.h>
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 533254a872..1712b8162c 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include <stdint.h> + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 |