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authorJoseph Smith <joe@settoplinux.org>2009-05-29 13:45:22 +0000
committerJoseph Smith <joe@smittys.pointclark.net>2009-05-29 13:45:22 +0000
commit60f0f1b18f87332a569ced6c8744a1572517ba39 (patch)
tree8a278fad3d544363b676e11800e38365a71b2b11 /src/southbridge/intel/i82801xx/chip.h
parentf8a5c6ec02f1e21d62756bda07f755b3a2f4865f (diff)
downloadcoreboot-60f0f1b18f87332a569ced6c8744a1572517ba39.tar.xz
enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801xx/chip.h')
-rw-r--r--src/southbridge/intel/i82801xx/chip.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h
index d86c07e8e0..d159aa2be0 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801xx/chip.h
@@ -43,6 +43,8 @@ struct southbridge_intel_i82801xx_config {
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
+ uint8_t ide0_enable;
+ uint8_t ide1_enable;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;