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authorUwe Hermann <uwe@hermann-uwe.de>2007-06-19 22:47:11 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-06-19 22:47:11 +0000
commitdfb3c130d5cdd3a01531c23c3d15e7a1010bf221 (patch)
tree625092b43a0c3ac24fa359eb14df0f922f81e6ad /src/southbridge/intel/i82801xx/chip.h
parentc72ff11281233c097441e809a52b560b1a131196 (diff)
downloadcoreboot-dfb3c130d5cdd3a01531c23c3d15e7a1010bf221.tar.xz
Various minor cosmetics and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801xx/chip.h')
-rw-r--r--src/southbridge/intel/i82801xx/chip.h17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h
index 3c1a3fd6d9..8896e3af56 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801xx/chip.h
@@ -19,21 +19,20 @@
*/
#ifndef IGNORE_I82801XX_DEVICE_LIST
-#warning "The i82801xx code currently supports, on a testing/experimental basis,"
-#warning "these devices:"
-#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm, i82801eb,"
-#warning "and i82801er."
-#warning "Using this without modification on any other i82801 version will probably"
-#warning "work until ram init, but will fail after that"
+#warning "The i82801xx code currently supports, on a testing/experimental"
+#warning "basis, these devices:"
+#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm,"
+#warning "i82801eb, and i82801er."
+#warning "Using this without modification on any other i82801 version will"
+#warning "probably work until RAM init, but will fail after that."
#endif
#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
-struct southbridge_intel_i82801xx_config
-{
+struct southbridge_intel_i82801xx_config {
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
-#endif /* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */