diff options
| author | Joseph Smith <joe@smittys.pointclark.net> | 2007-10-30 21:55:11 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-10-30 21:55:11 +0000 |
| commit | 68d8a56cc56ab9805bee85c08f7211ef8455ca4d (patch) | |
| tree | 9f47b9ccf67f54a8ce95b67c4e225f1f7e3a4474 /src/southbridge/intel/i82801xx/i82801xx.h | |
| parent | c4590dae6aaed753ecac00351262936084807d48 (diff) | |
| download | coreboot-68d8a56cc56ab9805bee85c08f7211ef8455ca4d.tar.xz | |
Various fixes and improvements of the 82801xx code.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801xx/i82801xx.h')
| -rw-r--r-- | src/southbridge/intel/i82801xx/i82801xx.h | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801xx/i82801xx.h index fa306bc0a4..41179c9640 100644 --- a/src/southbridge/intel/i82801xx/i82801xx.h +++ b/src/southbridge/intel/i82801xx/i82801xx.h @@ -33,21 +33,30 @@ extern void i82801xx_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 -#define PCICMD 0x04 #define PMBASE 0x40 -#define PM_BASE_ADDR 0x1100 #define ACPI_CNTL 0x44 #define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 -#define GPIO_BASE_ADDR 0x1180 -#define GPIO_CNTL 0x5C +#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ +#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */ +#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */ +#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */ + #define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 #define PIRQE_ROUT 0x68 -#define COM_DEC 0xE0 -#define LPC_EN 0xE6 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + #define FUNC_DIS 0xF2 -#define CMD 0x04 +#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */ +#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */ +#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */ + #define SBUS_NUM 0x19 #define SUB_BUS_NUM 0x1A #define SMLT 0x1B |