Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"

This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af

Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2
Reviewed-on: http://review.coreboot.org/3443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 0 insertions, 83 deletions

diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
deleted file mode 100644
index 708a7684b8..0000000000
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ /dev/null
@@ -1,83 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE+=ibexpeak_add_me
-
-ramstage-y += pch.c
-ramstage-y += azalia.c
-ramstage-y += lpc.c
-ramstage-y += pci.c
-ramstage-y += pcie.c
-ramstage-y += sata.c
-ramstage-y += usb_ehci.c
-ramstage-y += usb_xhci.c
-ramstage-y += me.c
-ramstage-y += smbus.c
-ramstage-y += thermal.c
-
-ramstage-y += me_status.c
-ramstage-y += reset.c
-ramstage-y += watchdog.c
-
-ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-y += spi.c
-ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
-smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
-smm-$(CONFIG_USBDEBUG) += usb_debug.c
-
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
-
-romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
-romstage-$(CONFIG_USBDEBUG) += usb_debug.c
-ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
-smm-$(CONFIG_USBDEBUG) += usb_debug.c
-romstage-y += reset.c
-romstage-y += early_spi.c
-
-ibexpeak_add_me: $(obj)/coreboot.pre $(IFDTOOL)
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-ifeq ($(CONFIG_HAVE_GBE_BIN),y)
-	printf "    IFDTOOL    gbe.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i GbE:$(CONFIG_GBE_BIN_PATH) \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-PHONY += ibexpeak_add_me