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authorStefan Reinauer <stefan.reinauer@coreboot.org>2013-06-13 00:13:50 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-06-13 00:27:07 +0200
commit3a09179f462ad3f6111c7b8ebbad7d78534f9234 (patch)
treeb854e11a926e555a4ade85950846b8cdea0ce56b /src/southbridge/intel/ibexpeak/chip.h
parent0210119b4b95e84f954cfd6dc11aafbc187421af (diff)
downloadcoreboot-3a09179f462ad3f6111c7b8ebbad7d78534f9234.tar.xz
Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2 Reviewed-on: http://review.coreboot.org/3443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/chip.h')
-rw-r--r--src/southbridge/intel/ibexpeak/chip.h103
1 files changed, 0 insertions, 103 deletions
diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h
deleted file mode 100644
index 83248d5a9a..0000000000
--- a/src/southbridge/intel/ibexpeak/chip.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H
-#define SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H
-
-struct southbridge_intel_ibexpeak_config {
- /**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
-
- /**
- * GPI Routing configuration
- *
- * Only the lower two bits have a meaning:
- * 00: No effect
- * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
- * 10: SCI (if corresponding GPIO_EN bit is also set)
- * 11: reserved
- */
- uint8_t gpi0_routing;
- uint8_t gpi1_routing;
- uint8_t gpi2_routing;
- uint8_t gpi3_routing;
- uint8_t gpi4_routing;
- uint8_t gpi5_routing;
- uint8_t gpi6_routing;
- uint8_t gpi7_routing;
- uint8_t gpi8_routing;
- uint8_t gpi9_routing;
- uint8_t gpi10_routing;
- uint8_t gpi11_routing;
- uint8_t gpi12_routing;
- uint8_t gpi13_routing;
- uint8_t gpi14_routing;
- uint8_t gpi15_routing;
-
- uint32_t gpe0_en;
- uint16_t alt_gp_smi_en;
-
- /* IDE configuration */
- uint32_t ide_legacy_combined;
- uint32_t sata_ahci;
- uint8_t sata_port_map;
- uint32_t sata_port0_gen3_tx;
- uint32_t sata_port1_gen3_tx;
-
- /**
- * SATA Interface Speed Support Configuration
- *
- * Only the lower two bits have a meaning:
- * 00 - No effect (leave as chip default)
- * 01 - 1.5 Gb/s maximum speed
- * 10 - 3.0 Gb/s maximum speed
- * 11 - 6.0 Gb/s maximum speed
- */
- uint8_t sata_interface_speed_support;
-
- uint32_t gen1_dec;
- uint32_t gen2_dec;
- uint32_t gen3_dec;
- uint32_t gen4_dec;
-
- /* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
-
- /* Override PCIe ASPM */
- uint8_t pcie_aspm_f0;
- uint8_t pcie_aspm_f1;
- uint8_t pcie_aspm_f2;
- uint8_t pcie_aspm_f3;
- uint8_t pcie_aspm_f4;
- uint8_t pcie_aspm_f5;
- uint8_t pcie_aspm_f6;
- uint8_t pcie_aspm_f7;
-};
-
-#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_CHIP_H */