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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-10 15:50:04 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2019-10-13 12:46:18 +0000 |
commit | 2882253237f254d5f78b7531ef3cefb974cd4bbb (patch) | |
tree | 91216e1814cff2806f15c503155d3ad3446cc48e /src/southbridge/intel/ibexpeak/early_pch.c | |
parent | b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (diff) | |
download | coreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.tar.xz |
nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
existing bootblock_mainboard_early_init().
Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/early_pch.c')
-rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ccd8f74431..b76115bf84 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -22,45 +22,6 @@ #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> -#include "chip.h" - -static void early_lpc_init(void) -{ - const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_ibexpeak_config *config = NULL; - - /* Add some default decode ranges: - - 0x2e/2f, 0x4e/0x4f - - EC/Mouse/KBC 60/64, 62/66 - - 0x3f8 COMA - If more are needed, update in mainboard_lpc_init hook - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - /* Clear PWR_FLR */ - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); - - pci_write_config32(PCH_LPC_DEV, ETR3, - pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); - - /* Set up generic decode ranges */ - if (!dev) - return; - if (dev->chip_info) - config = dev->chip_info; - if (!config) - return; - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); -} - static void early_gpio_init(void) { pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); @@ -80,12 +41,6 @@ static void pch_default_disable(void) RCBA32(FD2) = 1; } -void pch_pre_console_init(void) -{ - early_lpc_init(); - mainboard_lpc_init(); -} - void early_pch_init(void) { early_gpio_init(); |