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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 09:46:42 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:18:46 +0000 |
| commit | 7b2646536a773f181f766fe755403a242e9f3e8e (patch) | |
| tree | ba8ea9da5480943432e456a399e4e80a9744fa5b /src/southbridge/intel/ibexpeak/pch.c | |
| parent | b30d0545843b6ba3e8c0976a1fc0f1413be1608b (diff) | |
| download | coreboot-7b2646536a773f181f766fe755403a242e9f3e8e.tar.xz | |
util/intelmetool: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I3a00db217ce7acd11f979e64bb5d417a8bfc8717
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.c')
0 files changed, 0 insertions, 0 deletions