diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 09:58:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:20:53 +0000 |
| commit | 8b6dfdeb203c5e10c804398b822f85df2b4b6d26 (patch) | |
| tree | e9d67db357a2c50b7fa7633d2847afb20e4591c5 /src/southbridge/intel/ibexpeak/pch.c | |
| parent | 7b2646536a773f181f766fe755403a242e9f3e8e (diff) | |
| download | coreboot-8b6dfdeb203c5e10c804398b822f85df2b4b6d26.tar.xz | |
sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I212ef304a03d068232f50a71c318e2b468336339
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.c')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 29c3a7635b..5a15e3d968 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -66,24 +66,22 @@ static void pch_disable_devfn(struct device *dev) void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Disable this device if possible */ pch_disable_devfn(dev); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } |