sb/intel/ibexpeak: Implement PCH function disable in chip_ops

This does the following:
- implement a PCH disable function that will be called by the PCI
  drivers as part of their chip_ops
- removes the iobp_x calls as those don't exist on ibexpeak
- complete the devicetree with to be disabled PCI devices for the
  chip_ops to be called
- Clean up some code copied from bd82x6x

Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 107 insertions, 0 deletions

diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c
new file mode 100644
index 0000000000..9148b44a8e
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/pch.c
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include "pch.h"
+
+/* Set bit in function disable register to hide this device */
+static void pch_disable_devfn(struct device *dev)
+{
+	switch (dev->path.pci.devfn) {
+	case PCI_DEVFN(22, 0): /* MEI #1 */
+		RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+		break;
+	case PCI_DEVFN(22, 1): /* MEI #2 */
+		RCBA32_OR(FD2, PCH_DISABLE_MEI2);
+		break;
+	case PCI_DEVFN(22, 2): /* IDE-R */
+		RCBA32_OR(FD2, PCH_DISABLE_IDER);
+		break;
+	case PCI_DEVFN(22, 3): /* KT */
+		RCBA32_OR(FD2, PCH_DISABLE_KT);
+		break;
+	case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
+		RCBA32_OR(BUC, PCH_DISABLE_GBE);
+		break;
+	case PCI_DEVFN(26, 0): /* EHCI #2 */
+		RCBA32_OR(FD, PCH_DISABLE_EHCI2);
+		break;
+	case PCI_DEVFN(27, 0): /* HD Audio Controller */
+		RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
+		break;
+	case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
+	case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
+	case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
+	case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
+	case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
+	case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
+	case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
+	case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
+		RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
+		break;
+	case PCI_DEVFN(29, 0): /* EHCI #1 */
+		RCBA32_OR(FD, PCH_DISABLE_EHCI1);
+		break;
+	case PCI_DEVFN(31, 0): /* LPC */
+		RCBA32_OR(FD, PCH_DISABLE_LPC);
+		break;
+	case PCI_DEVFN(31, 2): /* SATA #1 */
+		RCBA32_OR(FD, PCH_DISABLE_SATA1);
+		break;
+	case PCI_DEVFN(31, 3): /* SMBUS */
+		RCBA32_OR(FD, PCH_DISABLE_SMBUS);
+		break;
+	case PCI_DEVFN(31, 5): /* SATA #22 */
+		RCBA32_OR(FD, PCH_DISABLE_SATA2);
+		break;
+	case PCI_DEVFN(31, 6): /* Thermal Subsystem */
+		RCBA32_OR(FD, PCH_DISABLE_THERMAL);
+		break;
+	}
+}
+
+void pch_enable(struct device *dev)
+{
+	u32 reg32;
+
+	if (!dev->enabled) {
+		printk(BIOS_DEBUG, "%s: Disabling device\n",  dev_path(dev));
+
+		/* Ensure memory, io, and bus master are all disabled */
+		reg32 = pci_read_config32(dev, PCI_COMMAND);
+		reg32 &= ~(PCI_COMMAND_MASTER |
+			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+		pci_write_config32(dev, PCI_COMMAND, reg32);
+
+		/* Disable this device if possible */
+		pch_disable_devfn(dev);
+	} else {
+		/* Enable SERR */
+		reg32 = pci_read_config32(dev, PCI_COMMAND);
+		reg32 |= PCI_COMMAND_SERR;
+		pci_write_config32(dev, PCI_COMMAND, reg32);
+	}
+}
+
+struct chip_operations southbridge_intel_ibexpeak_ops = {
+	CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge")
+	.enable_dev = pch_enable,
+};