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authorArthur Heymans <arthur@aheymans.xyz>2019-10-10 15:50:04 +0200
committerNico Huber <nico.h@gmx.de>2019-10-13 12:46:18 +0000
commit2882253237f254d5f78b7531ef3cefb974cd4bbb (patch)
tree91216e1814cff2806f15c503155d3ad3446cc48e /src/southbridge/intel/ibexpeak/pch.h
parentb9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (diff)
downloadcoreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.tar.xz
nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes: - Microcode init is done in assembly during the CAR init. - The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size against which the romstage stack guards protected. - The romstage mainboard_lpc_init() hook is removed in favor of the existing bootblock_mainboard_early_init(). Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.h')
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 1449ee914d..9e5fa24e9f 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -62,13 +62,11 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
#endif
-void pch_pre_console_init(void);
void early_pch_init(void);
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
void pch_setup_cir(int chipset_type);
-void mainboard_lpc_init(void);
enum current_lookup_idx {
IF1_F57 = 0,