diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/ibexpeak/pch.h | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.h')
-rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 13579460dc..9b2dd8ac8e 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -62,7 +62,7 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void gpi_route_interrupt(u8 gpi, u8 mode); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void pch_log_state(void); #endif #else /* __PRE_RAM__ */ |