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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-02 00:21:01 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:13:21 +0000 |
commit | d0310faa3bc4d3b62d17d632fbaee98c146eebe0 (patch) | |
tree | 8d3a55eb4135484ae7729f8092876ba36c165a2e /src/southbridge/intel/ibexpeak/pch.h | |
parent | f266dc61743cfce56ea026e66bc88cad8e5de2bb (diff) | |
download | coreboot-d0310faa3bc4d3b62d17d632fbaee98c146eebe0.tar.xz |
sb/intel/ibexpeak: Implement PCH function disable in chip_ops
This does the following:
- implement a PCH disable function that will be called by the PCI
drivers as part of their chip_ops
- removes the iobp_x calls as those don't exist on ibexpeak
- complete the devicetree with to be disabled PCI devices for the
chip_ops to be called
- Clean up some code copied from bd82x6x
Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/pch.h')
-rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index f0e469a3ac..34f80330bc 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -51,9 +51,6 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_smbus(void); void enable_usb_bar(void); |