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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-13 00:13:50 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-13 00:27:07 +0200 |
| commit | 3a09179f462ad3f6111c7b8ebbad7d78534f9234 (patch) | |
| tree | b854e11a926e555a4ade85950846b8cdea0ce56b /src/southbridge/intel/ibexpeak/usb_debug.c | |
| parent | 0210119b4b95e84f954cfd6dc11aafbc187421af (diff) | |
| download | coreboot-3a09179f462ad3f6111c7b8ebbad7d78534f9234.tar.xz | |
Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af
Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2
Reviewed-on: http://review.coreboot.org/3443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/usb_debug.c')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/usb_debug.c | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/src/southbridge/intel/ibexpeak/usb_debug.c b/src/southbridge/intel/ibexpeak/usb_debug.c deleted file mode 100644 index 3ef6d43fac..0000000000 --- a/src/southbridge/intel/ibexpeak/usb_debug.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <console/console.h> -#include <usbdebug.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include "pch.h" -#include <delay.h> -#if !defined (__PRE_RAM__) && !defined (__SMM__) -#define PCI_DEV(bus, dev, fn) dev_find_slot (bus, PCI_DEVFN (dev, fn)) -#endif - - -void enable_usbdebug(unsigned int port) -{ - u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1a, 0); /* USB EHCI, D29:F7 */ - device_t bdev = PCI_DEV(0, 0, 0); /* USB EHCI, D29:F7 */ - - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); - - pci_write_config16(bdev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); - dbgctl |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); -} - -/* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) -{ - /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ -} - |