diff options
author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-07 00:17:25 +0200 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-12 05:31:04 +0200 |
commit | 0210119b4b95e84f954cfd6dc11aafbc187421af (patch) | |
tree | 7ae26ebe87e407f294e6a947fb2bd19286bc5fbe /src/southbridge/intel/ibexpeak/watchdog.c | |
parent | 26419285bf6643776d5ad6534db7d0422758efb2 (diff) | |
download | coreboot-0210119b4b95e84f954cfd6dc11aafbc187421af.tar.xz |
Add support for Intel Ibex Peak (Mobile 5) southbridge
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3397
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/watchdog.c')
-rw-r--r-- | src/southbridge/intel/ibexpeak/watchdog.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/watchdog.c b/src/southbridge/intel/ibexpeak/watchdog.c new file mode 100644 index 0000000000..b6d9223113 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/watchdog.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <watchdog.h> + + // + // Disable PCH Watchdog timer at SB_RCBA+0x3410 + // + // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; + // +void watchdog_off(void) +{ + device_t dev; + unsigned long value, base; + + /* Turn off the ICH7 watchdog. */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + + /* Enable I/O space. */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + + /* Get TCO base. */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + + /* Disable the watchdog timer. */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + + /* Clear TCO timeout status. */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + + printk(BIOS_DEBUG, "PCH watchdog disabled\n"); +} |