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authorNico Huber <nico.h@gmx.de>2018-11-14 00:00:35 +0100
committerNico Huber <nico.h@gmx.de>2019-01-06 15:54:19 +0000
commit9faae2b939d0c83632baeefe80bef1739e125018 (patch)
treea3d62f5f14994f1facc2389d189796a836bd8e81 /src/southbridge/intel/ibexpeak
parentd2f678d3bd6ca4c05fa5c652d6cdf4623543e576 (diff)
downloadcoreboot-9faae2b939d0c83632baeefe80bef1739e125018.tar.xz
Kconfig: Unify power-after-failure options
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h4
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c2
4 files changed, 4 insertions, 6 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 7e2254e4d1..bb6e22cb73 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -38,6 +38,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select HAVE_INTEL_CHIPSET_LOCKDOWN
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 24a217d284..3358633792 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -174,7 +174,7 @@ static void pch_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 35bf0caced..19add778f3 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -82,10 +82,6 @@ void southbridge_configure_default_intmap(void);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index e510f19b6c..d305635398 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -403,7 +403,7 @@ static void southbridge_smi_sleep(void)
u8 reg8;
u32 reg32;
u8 slp_typ;
- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values
u8 tmp70, tmp72;