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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 01:02:28 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-20 17:04:46 +0000
commitb21bffae0ce5dee5d316ad544ccc6dedbc4475a1 (patch)
tree5affe6f49cf0c7b7cb5b95d6cd5dd928d624dd8b /src/southbridge/intel/ibexpeak
parent65e5b100e2133a305ba1f471a23d75dc37a2224d (diff)
downloadcoreboot-b21bffae0ce5dee5d316ad544ccc6dedbc4475a1.tar.xz
sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
-rw-r--r--src/southbridge/intel/ibexpeak/early_smbus.c2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h3
-rw-r--r--src/southbridge/intel/ibexpeak/smbus.c2
3 files changed, 3 insertions, 4 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 7d8503bb7d..85f20a745c 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index d0f131482b..437259ca9b 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -22,11 +22,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 7e9aa57da8..01001c3bb5 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -59,7 +59,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |