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| author | Bill XIE <persmule@gmail.com> | 2017-08-22 16:26:22 +0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-08-30 10:32:00 +0000 |
| commit | d533b16669a3bacb19b2824e6b4bc76a2a18c92a (patch) | |
| tree | 2659ee2c6687da3047fe96699dc69ab5b4054bd8 /src/southbridge/intel/ibexpeak | |
| parent | f9267f9bcdcc98f4c1689de3c573feaee511f13d (diff) | |
| download | coreboot-d533b16669a3bacb19b2824e6b4bc76a2a18c92a.tar.xz | |
sb/intel/*: add option to lockdown chipset on normal boot path
On platforms with a PCH, some registers within host bridge should be
locked down on each normal boot path (done by either coreboot or
payload) and S3 resume (always done by coreboot).
A function to perform such locking is implemented in src/northbridge/
intel/*/finalize.c, and is designed as the handler of an #SMI triggered
with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only
triggered during s3 resume, and not on normal boot path. This problem
has beed discussed in
https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html .
This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/
intel/common/Kconfig is added to control the actual locking, which
depends on several compatibility flags, including
"HAVE_INTEL_CHIPSET_LOCKDOWN".
In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint"
have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected.
The change is only well tested on Sandy Bridge, my Lenovo x230.
Change-Id: I43d4142291c8737b29738c41e8c484328b297b55
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 12 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 41ace46f7f..4b78118e4d 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select ACPI_SATA_GENERATOR select HAVE_INTEL_FIRMWARE select SOUTHBRIDGE_INTEL_COMMON_GPIO + select HAVE_INTEL_CHIPSET_LOCKDOWN config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a152dfe8b9..bc50f94d6b 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -782,6 +782,17 @@ static void southbridge_fill_ssdt(device_t device) intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); } +static void lpc_final(struct device *dev) +{ + /* Call SMM finalize() handlers before resume */ + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) || + acpi_is_wakeup_s3()) { + outb(APM_CNT_FINALIZE, APM_CNT); + } + } +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -794,6 +805,7 @@ static struct device_operations device_ops = { .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, + .final = lpc_final, .enable = pch_lpc_enable, .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, |