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authorPatrick Rudolph <siro@das-labor.org>2016-02-06 18:12:28 +0100
committerMartin Roth <martinroth@google.com>2016-02-23 00:28:26 +0100
commit10104685c50d05353318932f183864f3fca37489 (patch)
tree072dbb9e7ca8ccf32a78adb7827f7a4b8fdfb893 /src/southbridge/intel/ibexpeak
parent273a8dca1f7896c73b812ecc2c6cd2572ac51d6a (diff)
downloadcoreboot-10104685c50d05353318932f183864f3fca37489.tar.xz
southbridge/intel/ibexpeak: Use common gpio.c
Use shared gpio code from common folder. Remove the now unused bd82x6x/gpio.c. Needs test on real hardware ! Change-Id: Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13616 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig1
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h16
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c1
4 files changed, 3 insertions, 17 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index ffc0a1692d..f12068c707 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select COMMON_FADT
select ACPI_SATA_GENERATOR
select HAVE_INTEL_FIRMWARE
+ select SOUTHBRIDGE_INTEL_COMMON_GPIO
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 2987ea9df7..41d3afbecd 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -42,7 +42,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-y += smi.c
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
-romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c
+romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c
romstage-y += ../bd82x6x/reset.c
romstage-y += ../bd82x6x/early_rcba.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 057214332d..07127fafbf 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -432,22 +432,6 @@ void southbridge_configure_default_intmap(void);
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
-/* ICH7 GPIOBASE */
-#define GPIO_USE_SEL 0x00
-#define GP_IO_SEL 0x04
-#define GP_LVL 0x0c
-#define GPO_BLINK 0x18
-#define GPI_INV 0x2c
-#define GPIO_USE_SEL2 0x30
-#define GP_IO_SEL2 0x34
-#define GP_LVL2 0x38
-#define GPIO_USE_SEL3 0x40
-#define GP_IO_SEL3 0x44
-#define GP_LVL3 0x48
-#define GP_RST_SEL1 0x60
-#define GP_RST_SEL2 0x64
-#define GP_RST_SEL3 0x68
-
/* ICH7 PMBASE */
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index fb9693036f..319f9946c8 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -32,6 +32,7 @@
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
#include "northbridge/intel/nehalem/nehalem.h"
+#include <southbridge/intel/common/gpio.h>
#include <arch/pci_mmio_cfg.h>
/* While we read PMBASE dynamically in case it changed, let's