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authorVladimir Serbinenko <phcoder@gmail.com>2014-01-09 23:41:48 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-01-23 19:49:39 +0100
commit1cd937b48c652206e0c62bba81afe5a2a829742a (patch)
treeb5e4688daa66a88ba10f8c2a711522ddccc1d2c4 /src/southbridge/intel/ibexpeak
parent82926e1d16ff2fd78d6dd3d2d65f35ed45145774 (diff)
downloadcoreboot-1cd937b48c652206e0c62bba81afe5a2a829742a.tar.xz
Ibexpeak: add missing thermal init.
Without it ME doesn't always start correctly and no temperature is reported, no fan management and so on. Change-Id: Iff71f3afbc35a1453a20d182890ae2d196c556bd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4636 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/ibexpeak')
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc2
-rw-r--r--src/southbridge/intel/ibexpeak/early_thermal.c47
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h1
3 files changed, 49 insertions, 1 deletions
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index a29129d55c..e7f7d99a31 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -45,7 +45,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
-romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c
+romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c
romstage-y += ../bd82x6x/reset.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c
new file mode 100644
index 0000000000..9d96a34877
--- /dev/null
+++ b/src/southbridge/intel/ibexpeak/early_thermal.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include "pch.h"
+
+/* Early thermal init, must be done prior to giving ME its memory
+ which is done at the end of raminit. */
+void early_thermal_init(void)
+{
+ device_t dev;
+
+ dev = PCI_DEV(0x0, 0x1f, 0x6);
+
+ /* Program address for temporary BAR. */
+ pci_write_config32(dev, 0x40, 0x40000000);
+ pci_write_config32(dev, 0x44, 0x0);
+
+ /* Activate temporary BAR. */
+ pci_write_config32(dev, 0x40,
+ pci_read_config32(dev, 0x40) | 5);
+
+ /* Perform init. */
+ write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+
+ /* Disable temporary BAR. */
+ pci_write_config32(dev, 0x40,
+ pci_read_config32(dev, 0x40) & ~1);
+ pci_write_config32(dev, 0x40, 0);
+}
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 356dd8ae28..df125f052d 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -78,6 +78,7 @@ int smbus_write_byte(unsigned device, unsigned address, u8 data);
int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
+void early_thermal_init(void);
#endif
#endif