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authorArthur Heymans <arthur@aheymans.xyz>2017-09-25 12:21:07 +0200
committerArthur Heymans <arthur@aheymans.xyz>2017-12-10 14:50:08 +0000
commitbddef0dae73676c44364cd9d53813144ce42198a (patch)
tree5f50270d1b42f2461eb323b1928a3b4f661bc5bd /src/southbridge/intel/lynxpoint/Kconfig
parentbf8db8d45b35181c84a163ab669f7a8d39ad5fec (diff)
downloadcoreboot-bddef0dae73676c44364cd9d53813144ce42198a.tar.xz
sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI
This introduces a Kconfig option to include common Intel SPI code. Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/Kconfig')
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 646d480dd8..8d5cbbf227 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -23,13 +23,13 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ select SOUTHBRIDGE_INTEL_COMMON_SPI
select IOAPIC
select HAVE_HARD_RESET
select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
- select SPI_FLASH
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
select RTC