diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 22:50:08 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 13:03:51 +0000 |
| commit | a82f06cb8fd5899a37b6b73ec682e8058f42a93e (patch) | |
| tree | 201955714cd32385223b17423122736f714daebc /src/southbridge/intel/lynxpoint/acpi/pch.asl | |
| parent | e15dc9eb1e4aa8ae87e398fb0d6eb895f4bb86d5 (diff) | |
| download | coreboot-a82f06cb8fd5899a37b6b73ec682e8058f42a93e.tar.xz | |
sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e683c752ce..40d206d3dd 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -67,8 +67,11 @@ Scope (\) // PCI Express Ports 0:1c.x #include <southbridge/intel/common/acpi/pcie.asl> -// USB 0:1d.0 and 0:1a.0 -#include "usb.asl" +// USB EHCI 0:1d.0 and 0:1a.0 +#include "ehci.asl" + +// USB XHCI 0:14.0 +#include "xhci.asl" // LPC Bridge 0:1f.0 #include "lpc.asl" |