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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 23:08:04 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 13:04:48 +0000 |
| commit | fe91192bf5f20e0d6f7f05d5b1166bd215614a99 (patch) | |
| tree | 2933dec2895d3e8f7b5bbc7f59fe1ec559bb9a20 /src/southbridge/intel/lynxpoint/acpi/pch.asl | |
| parent | 1fa487e1b32f94a8c009962365c00e0c19294647 (diff) | |
| download | coreboot-fe91192bf5f20e0d6f7f05d5b1166bd215614a99.tar.xz | |
haswell/lynxpoint: Drop remaining uses of `ISLP` method
There's no need to dynamically differentiate between traditional and Low
Power platforms at runtime, and doing so makes code reuse more complex.
Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 40d206d3dd..6829cff2c1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -10,12 +10,6 @@ Scope (\) { - // Return TRUE if chipset is LynxPoint-LP - Method (ISLP, 0, NotSerialized) - { - Return (CONFIG(INTEL_LYNXPOINT_LP)) - } - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. OperationRegion (IO_T, SystemIO, 0x800, 0x10) Field (IO_T, ByteAcc, NoLock, Preserve) |