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authorRyan Salsamendi <rsalsamendi@hotmail.com>2017-06-30 17:15:57 -0700
committerMartin Roth <martinroth@google.com>2017-07-02 18:54:39 +0000
commit0d9b360b42d39d211d62f0c213aae9e7cf3f2924 (patch)
treeb4e0b236cdade276520d9d92b29fb3efe4c7b442 /src/southbridge/intel/lynxpoint/azalia.c
parent0c731b512a6adf3aa9ecee5e89b6514e75ed6653 (diff)
downloadcoreboot-0d9b360b42d39d211d62f0c213aae9e7cf3f2924.tar.xz
southbridge/intel/lynxpoint: Fix undefined behavior
Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/azalia.c')
-rw-r--r--src/southbridge/intel/lynxpoint/azalia.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index 35dc63c5e8..0b1acdd409 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -48,7 +48,7 @@ static void azalia_pch_init(struct device *dev, u8 *base)
u16 reg16;
u32 reg32;
- if (RCBA32(0x2030) & (1 << 31)) {
+ if (RCBA32(0x2030) & (1UL << 31)) {
reg32 = pci_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01;
reg32 |= (1 << 25);
@@ -72,9 +72,9 @@ static void azalia_pch_init(struct device *dev, u8 *base)
(1 << 25) | (1 << 26))) {
reg32 = pci_read_config32(dev, 0x120);
if (pch_is_lp())
- reg32 &= ~(1 << 31);
+ reg32 &= ~(1UL << 31);
else
- reg32 |= (1 << 31);
+ reg32 |= (1UL << 31);
pci_write_config32(dev, 0x120, reg32);
}
@@ -101,7 +101,7 @@ static void azalia_pch_init(struct device *dev, u8 *base)
if (!pch_is_lp()) {
reg32 = pci_read_config32(dev, 0xd0);
- reg32 &= ~(1 << 31);
+ reg32 &= ~(1UL << 31);
pci_write_config32(dev, 0xd0, reg32);
}