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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2013-08-13 10:45:21 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 12:03:00 +0100 |
| commit | 287522749ececda35b52dc9b9e8e704e305ec888 (patch) | |
| tree | 9bf72bb1d0f2d14d25f09d4925b58790c25c80f9 /src/southbridge/intel/lynxpoint/chip.h | |
| parent | 190688c65f7c128f2dace3b600d1c0f2e56723ee (diff) | |
| download | coreboot-287522749ececda35b52dc9b9e8e704e305ec888.tar.xz | |
lynxpoint: Add configuration option for SATA gen3 DTLE registers
Allow DTLE DATA / EDGE registers to be configured in board-specific
devicetree.
Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65716
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/chip.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index bb4c0048c2..1b4ac2a355 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -72,6 +72,9 @@ struct southbridge_intel_lynxpoint_config { uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + /* SATA DEVSLP Mux * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 |