diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-24 18:03:18 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:37:36 +0000 |
| commit | 2aaf7c0a1d1a895805772fe5f878606161c8d3c5 (patch) | |
| tree | 5d590e1379ec8098b6a8040a5357075d309f86c9 /src/southbridge/intel/lynxpoint/chip.h | |
| parent | 2ead36334050ac692e64adc59a97320d8792adcc (diff) | |
| download | coreboot-2aaf7c0a1d1a895805772fe5f878606161c8d3c5.tar.xz | |
haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/chip.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index e30d4b4c21..40d0460419 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -47,7 +47,8 @@ struct southbridge_intel_lynxpoint_config { uint32_t sata_port0_gen3_dtle; uint32_t sata_port1_gen3_dtle; - /* SATA DEVSLP Mux + /* + * SATA DEVSLP Mux * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 */ @@ -67,12 +68,13 @@ struct southbridge_intel_lynxpoint_config { /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce; + /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; - /* Serial IO configuration */ - /* Put devices into ACPI mode instead of a PCI device */ + /* Put SerialIO devices into ACPI mode instead of a PCI device */ uint8_t sio_acpi_mode; + /* I2C voltage select: 0=3.3V 1=1.8V */ uint8_t sio_i2c0_voltage; uint8_t sio_i2c1_voltage; @@ -91,4 +93,4 @@ struct southbridge_intel_lynxpoint_config { bool docking_supported; }; -#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ |