diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-17 11:31:40 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-14 18:25:10 +0100 |
| commit | 74c0d05cf51e089357712b2c855f344caba680fb (patch) | |
| tree | 81ff5169a3b42ea32207ec783485508e1174f7ac /src/southbridge/intel/lynxpoint/chip.h | |
| parent | 045f153a4fe2b6e1cb193db01866218d0316f253 (diff) | |
| download | coreboot-74c0d05cf51e089357712b2c855f344caba680fb.tar.xz | |
lynxpoint: Update device IDs and clock gating setup
- Add device IDs for lynxpoint mobile and LP variants.
- Update the clock gating setup based on BWG
- Update the SATA programming based on BWG
- Add a DEVSLP0 mux config register
Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/chip.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 1e6195bb62..ffeb977534 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -69,6 +69,11 @@ struct southbridge_intel_lynxpoint_config { uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; + /* SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; uint32_t gen1_dec; uint32_t gen2_dec; |