haswell/lynxpoint: Use new PCH/PM helper functions

This makes use of the new functions from pmutil.c that take
care of the differences between -H and -LP chipsets.

It also adds support for the LynxPoint-LP GPE0 register block
and the SMI/SCI routing differences.

The FADT is updated to report the new 256 byte GPE0 block on
wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
block so that part is zeroed to prevent IASL and the kernel
from complaining about a mismatch.

This was tested on WTM2.  Unfortunately I am still unable to get an
SCI delivered from the EC but I suspect that is due to a magic
command needed to put the EC in ACPI mode.  Instead I verified that
all of the power management and GPIO registers were set to expected
values.

I also tested transitions into S3 and S5 from both the kernel and
by pressing the power button at the developer mode screen and they
all function as expected.

Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index ffeb977534..95bd087bdb 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -35,7 +35,7 @@ struct southbridge_intel_lynxpoint_config {
 	uint8_t pirqh_routing;
 
 	/**
-	 * GPI Routing configuration
+	 * GPI Routing configuration for LynxPoint-H
 	 *
 	 * Only the lower two bits have a meaning:
 	 * 00: No effect
@@ -60,8 +60,11 @@ struct southbridge_intel_lynxpoint_config {
 	uint8_t gpi14_routing;
 	uint8_t gpi15_routing;
 
-	uint32_t gpe0_en;
-	uint16_t alt_gp_smi_en;
+	uint32_t gpe0_en_1;
+	uint32_t gpe0_en_2;
+	uint32_t gpe0_en_3;
+	uint32_t gpe0_en_4;
+	uint32_t alt_gp_smi_en;
 
 	/* IDE configuration */
 	uint32_t ide_legacy_combined;