diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-14 11:16:34 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:27:53 +0100 |
| commit | 8d783b84930e2e14e4f70234ea6589acd06557e7 (patch) | |
| tree | d8aaf94f486d2935eb86cfacfa397fe16fa8a639 /src/southbridge/intel/lynxpoint/early_pch.c | |
| parent | 1c0540000dc4705cee44857293285382f4ae8bad (diff) | |
| download | coreboot-8d783b84930e2e14e4f70234ea6589acd06557e7.tar.xz | |
slippy: Minor vboot related fixes
- Disable EC software sync for now
- Report correct EC active firmware mode
- Force enable developer mode by default
- Set up PCH generic decode regions in romstage
- Pass the oprom_is_loaded flag into vboot handoff data
Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4169
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 7a24e1fb03..38506c9438 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,10 +20,12 @@ #include <console/console.h> #include <arch/io.h> +#include <device/device.h> #include <device/pci_def.h> #include <timestamp.h> #include <elog.h> #include "pch.h" +#include "chip.h" #if CONFIG_INTEL_LYNXPOINT_LP #include "lp_gpio.h" @@ -96,15 +98,29 @@ static int sleep_type_s3(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct southbridge_intel_lynxpoint_config *config = NULL; /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(dev, LPC_EN, lpc_config); + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + + /* Set up generic decode ranges */ + if (!dev) + return; + if (dev->chip_info) + config = dev->chip_info; + if (!config) + return; + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } int early_pch_init(const void *gpio_map, |