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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 10:13:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:22:27 +0000 |
| commit | 73ae076e954ea6acd2fd22386616cd4ce839c830 (patch) | |
| tree | fe4dfa4a69391000f117a09bae8f2d5551e98758 /src/southbridge/intel/lynxpoint/early_usb.c | |
| parent | 8b6dfdeb203c5e10c804398b822f85df2b4b6d26 (diff) | |
| download | coreboot-73ae076e954ea6acd2fd22386616cd4ce839c830.tar.xz | |
sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_usb.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_usb.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 2f28369d53..075892b580 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -25,11 +25,8 @@ */ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { - u32 cmd; pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - cmd = pci_read_config32(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } void enable_usb_bar(void) |