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author | Ryan Salsamendi <rsalsamendi@hotmail.com> | 2017-07-04 13:14:16 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-07-10 18:15:11 +0000 |
commit | 3f2fe18965fc5404e4d095a25dcb1be48e4040a5 (patch) | |
tree | f17cc962dad56d84ff9eb481564406e8fcced61d /src/southbridge/intel/lynxpoint/finalize.c | |
parent | 2fdf895867bc258690943475f0d2e8fc7daa6ee5 (diff) | |
download | coreboot-3f2fe18965fc5404e4d095a25dcb1be48e4040a5.tar.xz |
southbridge/intel/lynxpoint: Fix undefined behavior
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/finalize.c')
-rw-r--r-- | src/southbridge/intel/lynxpoint/finalize.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 1ff38e9280..79a0915671 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -40,7 +40,7 @@ void intel_pch_finalize_smm(void) #endif /* TCLOCKDN: TC Lockdown */ - RCBA32_OR(0x0050, (1 << 31)); + RCBA32_OR(0x0050, (1UL << 31)); /* BIOS Interface Lockdown */ RCBA32_OR(0x3410, (1 << 0)); @@ -55,7 +55,7 @@ void intel_pch_finalize_smm(void) pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* PMSYNC */ - RCBA32_OR(PMSYNC_CONFIG, (1 << 31)); + RCBA32_OR(PMSYNC_CONFIG, (1UL << 31)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); |