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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-29 11:32:27 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-04-28 07:59:13 +0200
commitb85a87b7d6f9f12d5c71c32741c8af731ed6be7e (patch)
tree67553a9c683557ead346dc1c7b155d3eac475090 /src/southbridge/intel/lynxpoint/lpc.c
parent189f3ba974df8f1b305cfa421a151fe069fc1a6f (diff)
downloadcoreboot-b85a87b7d6f9f12d5c71c32741c8af731ed6be7e.tar.xz
intel SMI handlers: Refactor GPI SMI/SCI routing
Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d753bea776..d83ec0a1f2 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -175,7 +175,7 @@ static void pch_gpi_routing(device_t dev)
reg32 |= (config->gpi14_routing & 0x03) << 28;
reg32 |= (config->gpi15_routing & 0x03) << 30;
- pci_write_config32(dev, 0xb8, reg32);
+ pci_write_config32(dev, GPIO_ROUT, reg32);
}
static void pch_power_options(device_t dev)