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author | Aaron Durbin <adurbin@chromium.org> | 2013-06-20 01:20:30 -0500 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-12-05 20:12:49 +0100 |
commit | c0254e6b6fbe7268fa47b2d4bd0a203423b2eec2 (patch) | |
tree | 4c94730bfe8b4adfa96aa076a97e65e8edcf9935 /src/southbridge/intel/lynxpoint/lpc.c | |
parent | 6e764ff1f1919f64cc76e699d875d50c8c22759c (diff) | |
download | coreboot-c0254e6b6fbe7268fa47b2d4bd0a203423b2eec2.tar.xz |
lynxpoint: disable pcie devices based on config
PCIe Root Ports should be disabled based on pin ownership
and the strapping configuration. Implement this logic
for LynxPoint. The chip_ops->enable_dev() path is no
longer used. Instead the PCIe driver handles the enabling
and disabling of devices. This allows for having an empty
or incomplete device tree since those "allocated" devices
do not travel through the chip_ops->enable_dev() path.
The coalescing was tested to be working properly, however
not all configurations were tested.
Change-Id: I1e8bfe5e447b72ff8a4b04b650982d8c1ae0823c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59424
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4322
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/lpc.c')
0 files changed, 0 insertions, 0 deletions