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| author | Frans Hendriks <fhendriks@eltan.com> | 2019-05-01 10:48:31 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2019-05-03 22:39:14 +0000 |
| commit | e6bf51fb221db651c271115b32f1308983d20987 (patch) | |
| tree | d5f5cb3ea260cc868f38e166707e7dd5cbfd791a /src/southbridge/intel/lynxpoint/pch.c | |
| parent | a88041c04315cd2875cdf71e8070a6c7faa355a3 (diff) | |
| download | coreboot-e6bf51fb221db651c271115b32f1308983d20987.tar.xz | |
{soc, southbridge} : Correct typo in comment
BUG=N/A
TEST=N/A
Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 5cf67aa238..a57bae311d 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -100,7 +100,7 @@ static void pch_enable_d3hot(struct device *dev) pci_write_config32(dev, PCH_PCS, reg32); } -/* Set bit in Function Disble register to hide this device */ +/* Set bit in function disable register to hide this device */ void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { |