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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-19 09:12:31 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 20:16:26 +0100 |
| commit | 26e7dd703dea8dce30829d8bb73c1f27a2178d72 (patch) | |
| tree | 924161b457fd106535444b45089d3e0ede1dd8d9 /src/southbridge/intel/lynxpoint/pch.c | |
| parent | eb58bc5af6b8bf626f38d0c07bf55db2835f53b5 (diff) | |
| download | coreboot-26e7dd703dea8dce30829d8bb73c1f27a2178d72.tar.xz | |
haswell: more ULT/LP support and minor tweaks
- Add ME device ID for Lynxpoint LP
- Add GPU device IDs for ULT
- SATA init tweaks from checking against DXE reference code
- Remove the ICH7 from the SPI driver so it works on all lynxpoint
without having to add more LPC device ID checks
- Add function disable for audio dsp and xhci, remove PCI bridge
- Add interrupt route registers for new devices (needs romstage setup)
Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2680
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index c2765e91eb..1fb49158ee 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -55,6 +55,12 @@ int pch_silicon_supported(int type, int rev) static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(19, 0): /* Audio DSP */ + RCBA32_OR(FD, PCH_DISABLE_ADSPD); + break; + case PCI_DEVFN(20, 0): /* XHCI */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; @@ -89,9 +95,6 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); break; - case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ - RCBA32_OR(FD, PCH_DISABLE_P2P); - break; case PCI_DEVFN(31, 0): /* LPC */ RCBA32_OR(FD, PCH_DISABLE_LPC); break; @@ -101,7 +104,7 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(31, 3): /* SMBUS */ RCBA32_OR(FD, PCH_DISABLE_SMBUS); break; - case PCI_DEVFN(31, 5): /* SATA #22 */ + case PCI_DEVFN(31, 5): /* SATA #2 */ RCBA32_OR(FD, PCH_DISABLE_SATA2); break; case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |