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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 00:12:43 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-07 11:02:43 +0000 |
| commit | bf9bc50ec1d1b54a9ae0b86fc1e37e013422186f (patch) | |
| tree | 71761d671564698f5386bceb501404a16924b380 /src/southbridge/intel/lynxpoint/pch.c | |
| parent | bd84485017a460fa23758770c547de2a859e2dff (diff) | |
| download | coreboot-bf9bc50ec1d1b54a9ae0b86fc1e37e013422186f.tar.xz | |
sb/intel/lynxpoint: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I27d6aaa59e12a337f80a6d3387cc9c8ae5949384
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42154
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 0a0e489d6f..2d2023b6a2 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -86,9 +86,7 @@ u16 get_gpiobase(void) /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) { - u32 reg32 = pci_read_config32(dev, PCH_PCS); - reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); + pci_or_config32(dev, PCH_PCS, PCH_PCS_PS_D3HOT); } /* Set bit in function disable register to hide this device */ @@ -291,8 +289,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) void pch_enable(struct device *dev) { - u16 reg16; - /* PCH PCIe Root Ports are handled in PCIe driver. */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) return; @@ -301,9 +297,8 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Disable this device if possible */ pch_disable_devfn(dev); |