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authorPaul Menzel <paulepanter@users.sourceforge.net>2013-05-03 12:17:02 +0200
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-06-03 08:22:59 +0200
commit373a20c335bdd747d7a2553f0e72e2b3a46f86e8 (patch)
tree358abee4123b7a062f71fff379818bc69d2025d2 /src/southbridge/intel/lynxpoint/pch.h
parent9c50e6a4a071a03c4dedd8eb87022644e9ee74c3 (diff)
downloadcoreboot-373a20c335bdd747d7a2553f0e72e2b3a46f86e8.tar.xz
Intel Lynx Point: LPC: Unify I/O APIC setup
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3182 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 21933b4660..c04957308f 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -236,6 +236,7 @@ unsigned get_gpios(const int *gpio_num_array);
#define PMBASE 0x40
#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 7)
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */