diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-06-19 13:28:04 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-02 15:09:08 +0100 |
| commit | 60f820835f66ad4eb63f2fdecb7ebce3411077a8 (patch) | |
| tree | a4ad2f35542a3a077520f1fa07bcdb881fbbea12 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | 3fcd356464bd65e8aafa0aae01e7fa6a2f4bc67d (diff) | |
| download | coreboot-60f820835f66ad4eb63f2fdecb7ebce3411077a8.tar.xz | |
lynxpoint: move all pcie device handling to pcie.c
Some of the pcie logic was located in pch.c as well
as pcie.c. Move all pcie logic to the same pcie.c
file. This is a straight cut-and-paste (no logic changes)
except for a rename from pch_pcie_enable() ->
pch_pcie_enable_dev().
Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59277
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4251
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7c187054cc..9acdd1f79c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -166,6 +166,7 @@ void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +void pch_pcie_enable_dev(device_t dev); #if CONFIG_ELOG void pch_log_state(void); #endif |