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author | Aaron Durbin <adurbin@chromium.org> | 2013-06-19 13:12:48 -0500 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-02 15:07:34 +0100 |
commit | c17aac32f27f6ab18faaabc8a5667bc2a0a10120 (patch) | |
tree | 56fac0fe0ca3fdf1eea832c2f42d7fcf3ac6abf8 /src/southbridge/intel/lynxpoint/pch.h | |
parent | 91bd0b8419d4949fd2aa447432f0d68352f20965 (diff) | |
download | coreboot-c17aac32f27f6ab18faaabc8a5667bc2a0a10120.tar.xz |
lynxpoint: expose iobp functions
The iobp functions are useful to may of the southbridge
devices as certain values need to be updated to properly
initialize the devices. Therefore expose read, write, and
updated iobp functions.
Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59275
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4249
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6ee81d1f4b..c46153ca44 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -162,6 +162,8 @@ void disable_gpe(u32 mask); #include <arch/acpi.h> #include "chip.h" void pch_enable(device_t dev); +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void); |