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authorDuncan Laurie <dlaurie@chromium.org>2013-04-26 10:35:19 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 16:04:12 +0100
commite1e87e0ed6280f168abd92edcd692aec4ead8fe8 (patch)
tree0545c568254811a9b8204ebd880539a689ae1fe5 /src/southbridge/intel/lynxpoint/pch.h
parentf24262d01822bd8634e44b5aab19dafe7e04ae72 (diff)
downloadcoreboot-e1e87e0ed6280f168abd92edcd692aec4ead8fe8.tar.xz
haswell: Configure PCH power sharing for ULT
This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4143 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 4bdb9268e9..58b07d16cc 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -574,6 +574,8 @@ void set_gpio(int gpio_num, int value);
#define D19IR 0x3168 /* 16bit */
#define ACPIIRQEN 0x31e0 /* 32bit */
#define OIC 0x31fe /* 16bit */
+#define PMSYNC_CONFIG 0x33c4 /* 32bit */
+#define PMSYNC_CONFIG2 0x33cc /* 32bit */
#define SOFT_RESET_CTRL 0x38f4
#define SOFT_RESET_DATA 0x38f8