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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-03-07 14:06:43 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:05:45 +0100 |
| commit | 5cc51c08cd44e2749f4a27775cefffd4b91e0a50 (patch) | |
| tree | f7ff55f3a2a6dadf8bf22630a015bb2153aff7c4 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | 7a3fd4de053e055ce6854e7ec42fb00da532d3d3 (diff) | |
| download | coreboot-5cc51c08cd44e2749f4a27775cefffd4b91e0a50.tar.xz | |
lynxpoint: Add function for checking for LP chipset
Add a helper function pch_is_lp() that will return 1 if
the current chipset is of the new "low power" variant used
with Haswell ULT.
Additionally these functions are added to SMM so it can
be used there.
Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2811
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 563730eae6..38202b5690 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -40,9 +40,9 @@ * Bus 0:Device 28:Function 5 PCI Express Port 6 * Bus 0:Device 28:Function 6 PCI Express Port 7 * Bus 0:Device 28:Function 7 PCI Express Port 8 - * Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller + * Bus 0:Device 27:Function 0 Intel High Definition Audio Controller * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller - * Bus 0:Device 22:Function 0 Intel® Management Engine Interface #1 + * Bus 0:Device 22:Function 0 Intel Management Engine Interface #1 * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2 * Bus 0:Device 22:Function 2 IDE-R * Bus 0:Device 22:Function 3 KT @@ -50,6 +50,8 @@ */ /* PCH types */ +#define PCH_TYPE_LPT 0x8c +#define PCH_TYPE_LPT_LP 0x9c /* PCH stepping values for LPC device */ @@ -125,13 +127,14 @@ struct rcba_config_instruction #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_is_lp(void); + #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> #include <arch/acpi.h> #include "chip.h" -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG |